1. Field of the Invention
The present invention relates to a method for optimizing a netlist used in the logic circuit design of a semiconductor integrated circuit, a device for assisting in the design of a logic circuit using this method, and a computer program executable by this device.
2. Related Art
When a semiconductor integrated circuit is designed, the logic circuit is first described at the register transfer level (RTL) in a hardware description language (HDL), and a netlist is generated through logical synthesis using a cell library for the arrangement (logical operation element grouping).
However, when placement and routing is performed based on the netlist after logical synthesis and the timing is analyzed, unexpected critical paths sometimes occur due to clock cycles, input/output delays and so on. In other words, when a certain logical operation element becomes a critical path, a deviation occurs in the overall operational timing, and it can become difficult to execute a logical operation properly.
Therefore, in the prior art, a netlist is generated by performing logical synthesis under conditions in which a higher frequency is used to provide a margin. Simply put, the logical synthesis is performed using a higher frequency. Patent Literature 1 discloses a logical synthesis device in which timing verification is performed using the processing speed between FF as the standard.